XCENA Unveils CXL Memory Solution at OCP 2026 to Ease AI Inference Bottlenecks
TECHWORLD ·
✦ AI Summary
XCENA unveiled its CXL-based memory solution MX1 and 2 AI inference demos at OCP Global Summit 2026.
At the SK hynix booth, it demonstrated KV cache sharing technology based on a CXL memory pool across multiple AI inference servers.
XCENA also demonstrated RAG vector search acceleration technology using MX1's NDP function, saying it aimed to ease AI inference bottlenecks through memory sharing and near-data processing.
XCENA said on the 16th that it has unveiled a CXL-based memory solution technology aimed at easing memory bottlenecks and data movement burdens in the AI inference process.
XCENA participated in OCP Global Summit 2026, held at the San Jose Convention Center in the United States. The event ran from the 12th to the 15th local time. OCP Global Summit is an event where global cloud, data center, semiconductor companies, and technology experts discuss next-generation computing infrastructure technologies and standards.
At the event, XCENA unveiled an AI inference demo and next-generation memory infrastructure technology using its CXL-based memory solution, MX1. On site, it demonstrated 2 AI inference demos using MX1.
At the SK hynix booth (A2), XCENA demonstrated a KV cache sharing technology based on a CXL memory pool across multiple AI inference servers.
In AI inference environments, KV cache stores prior processing information from AI models and reuses it when generating responses. Conventional KV cache operations used server-by-server storage. By contrast, CXL memory pool-based KV cache sharing allows multiple servers to use it jointly, reducing duplicate storage and easing the burden of data movement between servers.
XCENA demonstrated a RAG vector search acceleration technology using MX1's Near-Data Processing (NDP) function. This acceleration method performs searches directly in the memory where the data is stored, rather than repeatedly transferring large volumes of data to the host processor. As a result, it was presented as reducing data movement through direct memory search effects.
As AI inference services expand, memory capacity, bandwidth, latency caused by data movement, and system resource consumption have emerged as major challenges. XCENA focused on combining memory sharing with near-data processing. The goal is to ease bottlenecks and improve AI infrastructure efficiency.
XCENA and SK hynix are carrying out technical collaboration to apply CXL hybrid architecture to AI workloads. The two companies used InfiniteMemory®, MX1's SSD memory expansion feature. Verification results showed improved memory capacity scalability compared with CMM-D and confirmed that better performance than SSD could be achieved.
Based on these results, the two companies are verifying the technology's applicability in actual AI serving environments.
SK hynix unveiled a CXL hybrid memory and RDMA (Remote Direct Memory Access)-based architecture using the MX1 chip at the event. RDMA is a technology that directly accesses remote system memory and reduces processor involvement in the data transfer process.
The focus of the collaboration between the two companies is to secure both memory scalability and data access efficiency at the same time. The goal of the collaboration is to ease memory bottlenecks in AI inference environments.
During the event, XCENA participated in discussions with global companies on next-generation memory technologies and the software ecosystem. XCENA also carried out its technical discussions, presentations, and panel schedules during the event.
On the 14th, Kim Ju-hyeon, XCENA's CPO, gave a presentation. The topic was 'Bringing General-Purpose Parallel Programming to Near-Data Processing.' Kim Ju-hyeon, CPO, also joined a panel discussion with Marvell, Samsung Electronics, SK hynix, and GoTravis Technologies on open middleware for hyperscale heterogeneous AI infrastructure.
On the 15th, XCENA and Samsung Electronics gave a joint presentation. The topic was 'Disaggregated CXL Memory Architecture for Agentic AI: Dynamic Pooling, Sharing, and PNM Offloading.'
The architecture addresses dynamic allocation and sharing of memory resources and offloading of processor-adjacent memory processing (PNM). Its core purpose is to improve memory resource utilization and processing efficiency in Agentic AI environments.
The architecture targets environments in which a variety of tasks are carried out sequentially. In environments like Agentic AI, where multiple tasks proceed one after another, the issues surrounding memory allocation and sharing, as well as PNM offloading, were carried into an OCP Composable Memory Systems (CMS) subproject technical update session.
On the 15th, Grant Mackey, Distinguished Engineer at XCENA, joined an OCP Composable Memory Systems (CMS) subproject technical update session with representatives from Microsoft, Seagate, and Meta. The session was titled 'Addressing Memory Wall Challenge for AI and General Compute Platforms,' and discussed the current status of CMS technology development to address rising memory capacity demands in AI and general compute environments, the current status of CMS technology development to address rising memory bandwidth demands in AI and general compute environments, and the future direction of CMS technology.
Kim Jin-young, CEO of XCENA, said that to improve the performance and efficiency of AI infrastructure, it is essential not only to boost computing performance but also to use memory efficiently and minimize data movement. From that perspective, he said the company showcased the practical applicability of MX1 to real AI workloads at this event and expressed its intention to continue developing next-generation AI memory infrastructure in cooperation with partners across the ecosystem.
Source: TECHWORLD · Park Gyu-chan
Original: https://www.epnc.co.kr/news/articleView.html?idxno=408302
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Source: TECHWORLD
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