“Safety Implementation Matters More Than Speed”: PCIe Fast-Track Reliability Verification Gains Ground
TECHWORLD ·
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As data throughput rises across HPC, AI, and data centers, PCIe transmission speeds are also moving faster, and the importance of verification technologies for stable implementation is growing.
Teledyne LeCroy held the "PCIe & CXL Summit 2026" on the 17th to share PCIe and CXL technology trends and PCIe 6.0 and 7.0 verification challenges.
At the event, the need for verification that takes actual system environments into account was discussed, along with the unveiling of the "Summit Z74 Exerciser."
As data throughput rises across HPC, AI, and data centers, PCIe (PCI Express) transmission speeds are also moving faster. As a result, the importance of verification technologies for stable implementation is expanding.
Existing measurement methods have their limits. Even devices that meet the specification can run into connection problems, and the industry says verification that takes actual system environments into account is needed.
Against this backdrop, Teledyne LeCroy held the "PCIe & CXL Summit 2026" on the 17th. At the event, PCIe and CXL technology trends and the main verification challenges for next-generation high-speed interfaces were shared.
Teledyne LeCroy, Anritsu, Synopsys, and AMD took part in the event, and industry experts delivered session presentations. The topics covered PCIe 6.0 and 7.0 verification technologies and the direction of PCIe and CXL deployment in the AI era.
The presentations were organized around PCIe 6.0 and 7.0 testing and countermeasures, CXL integration, and applications in AI- and data-centric systems. Session topics included PCIe 6.0 electrical compliance and PCIe 7.0 countermeasures, PCIe Gen6 and 7 receiver (Rx) testing, PCIe and CXL technology and application trends in the AI era, PCIe Gen6 and CXL 3.1 connectivity for next-generation data-centric systems, and PCIe 7.0 protocol testing.
PCIe is becoming faster with each generation. PCIe transmission speeds have doubled roughly every 3 years, with PCIe 5.0 at 32GT/s, PCIe 6.0 at 64GT/s, and PCIe 7.0 at 128GT/s, while the development target for PCIe 8.0 is 256GT/s. The drive to speed up from PCIe 6.0 to 7.0 is continuing as well.
As speeds rise, the scope of verification is also expanding. Verification targets are broadening to include signal integrity, receiver testing, link training, protocols, and interoperability, and the need for reliability measures tailored to PCIe fast-track implementation has come into focus.
As transmission speeds increase, it is becoming harder to deliver signals safely and measure them accurately. Starting with PCIe 6.0, PAM4 replaced NRZ, and PAM4 is a method that transmits 2 bits per symbol across 4 voltage levels. As a result of PAM4 adoption, the voltage margin between signal levels has narrowed, amplifying the impact of channel loss, noise, and jitter.
Patrick Connally, senior product marketing manager at Teledyne LeCroy, said in the first session that after the transition to Gen6, it was confirmed that the accuracy of existing methods was insufficient and that repeatability was lacking across different measurement environments. He presented the main electrical tests for PCIe 6.0's 64GT/s PAM4 signals and the issues that can arise during actual verification, and said oscilloscope noise can cause a 1 to 3 dB difference in SNDR measurements. He added that, depending on the case, the difference can determine whether a test passes or fails.
As PCIe speeds up, not only the measurement targets but also the instruments and measurement procedures themselves are becoming more sophisticated. Accordingly, measurement methods are being advanced to precisely confirm electrical characteristics.
Transmitter verification methods are also changing from one generation to the next. For transmitter equalization measurements, an LFPR-based method has been applied since PCIe 6.0, and PCIe 7.0 uses 6 toggle patterns to measure transmitter jitter. For future PCIe 8.0 verification, methods that separate vertical noise effects before checking timing jitter are being discussed, and the candidate approaches presented were "Timing-only" and "Phase-only."
In receiver verification, the importance of precisely reproducing channel loss, jitter, and noise that can occur in actual systems is growing. The goal of receiver verification is to determine whether signals can be properly accepted even under worst-case conditions.
According to the presentation, the initial operating speed of a PCIe 7.0 link is not 128GT/s. A PCIe 7.0 link starts at 2.5GT/s and uses a method that reaches the target speed after negotiating speeds at each stage. In this process, link training and equalization are carried out as the speed increases, and if problems occur, the link can enter the Recovery state and may operate at a lower speed.
Gordon Getty, director of product management for protocol solutions at Teledyne LeCroy, said in a session titled "PCIe 7.0 Protocol Testing" that checking PCIe 7.0 verification based only on the final operating speed is insufficient. He said it is necessary to trace the entire link formation process and also to identify where problems occur.
Gordon Getty said the role of retimers is expanding as channel limits widen. He also said that when multiple retimers are used, signal regeneration is performed for each segment and equalization is also carried out by segment, adding that multi-retimer deployments increase verification points.
Against this backdrop, the industry sees that as PCIe moves from 128GT/s for 7.0 to 256GT/s for 8.0, measuring electrical characteristics for specification compliance alone is not enough to address issues caused by faster speeds. Accordingly, demand is growing for verification of stable operation in real system environments, and the industry expects that as PCIe speeds continue to rise, the importance of measurement accuracy and verification capabilities for ensuring system-level interoperability will expand.
Teledyne LeCroy said it unveiled the industry's first protocol system for PCIe 7.0 debugging and verification, the "Summit Z74 Exerciser," on the day. The product is a solution that provides the necessary control and visibility for PCIe 7.0 environments, helping engineering teams identify interoperability issues caused by PCIe speed increases in advance, shorten debug cycles, and reduce development risk.
Source: TECHWORLD · Kim Hye-jin
Original: https://www.epnc.co.kr/news/articleView.html?idxno=407128
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Source: TECHWORLD
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