Microchip Lowers Voltage Barrier for Advanced SoCs With 1.2V Clock Buffer

Microchip Technology has unveiled a 1.2V LVCMOS clock buffer lineup designed to provide stable low-voltage clock signals for advanced semiconductors. On the 9th, the company announced the launch of the 1.2V-output LVCMOS clock buffer family, "SY757xx."

Recently, the adoption of FinFET-based advanced processes has expanded, centered on high-performance FPGA, SoC, AI accelerators, and next-generation CPUs. As FinFET-based advanced process adoption has expanded, demand for low-voltage clock drivers has also risen.

As a result of these changes, PCB design stages now require solutions that convert high-voltage clock signals into the low-voltage levels demanded by advanced devices, in addition to existing 1.2V LVCMOS clock buffers. This is the background behind the growing importance of voltage conversion tools beyond simply supplying buffers.

In existing approaches, voltage was lowered using discrete components or voltage divider circuits. However, such methods carry the risk of duty cycle distortion and degraded signal integrity.

Existing approaches also lead to an increase in component count. A higher component count is cited as a factor that increases PCB design complexity and creates cost burdens.

Microchip says it aims to solve clock voltage conversion and distribution issues with a single chip through its SY757xx family. The family is designed to support clock voltage conversion and distribution.

The SY757xx family supports a wide supply voltage (VDD) range and a wide operating frequency range. It can also convert voltage levels from various clock sources to 1.2V to 1.8V LVCMOS outputs, and some products support input signals in the 1.2V to 3.3V range.

This allows 3.3V clock signals to be connected to FPGA and SoC devices that require 1.2V clock inputs. As a result, no separate voltage divider circuit is needed, and no discrete components are needed either.

In addition, the SY757xx family supports a frequency range of 0Hz to 250MHz, and its additive jitter is as low as 26 fs. The family is designed to ensure clock timing accuracy and signal integrity in high-speed digital systems.

Microchip says that, compared with conventional discrete approaches, a dedicated clock buffer-based approach can deliver optimized AC coupling and biasing, as well as BOM cost savings. It also said that using a voltage divider circuit may make it difficult to secure sufficient design margin and could cause duty cycle distortion. Accordingly, the company said that using a dedicated clock buffer can reduce design burden.

The SY757xx family is intended for clock distribution and fanout in FPGA and SoC applications. Target applications include embedded vision and video processing, AI and machine learning acceleration, industrial control and IoT, networking and communications, signal processing, and embedded systems.

The SY757xx family consists of 11 models in total. Of these, 3 are in mass production, and 8 are being supplied as limited-quantity samples.

The SY757xx family uses 8-pin VDFN and TDFN packages. These space-saving packages help reduce PCB area.

Mamoun Abou Seido, vice president of Microchip's Timing and Communications business unit, said the SY757xx clock buffer family helps address the growing clock distribution challenges of next-generation high-performance FPGA, SoC, and CPU platforms, and that by combining ultra-low-power additive jitter with broad VDD and frequency support in a single chip, it can simplify board design and reduce component count while maintaining signal integrity and timing accuracy.

Source: TECHWORLD · Park Gyu-chan
Original: https://www.epnc.co.kr/news/articleView.html?idxno=406723

References

• https://www.epnc.co.kr/news/articleView.html?idxno=406723