[Tech Report] More Current in Less Space... Dual-Phase DrMOS for the AI Era
TECHWORLD ·
✦ Resumen de IA
As generative AI and LLMs spread, power demand from data centers and AI processors is growing, raising the challenge of power design that simultaneously addresses power conversion efficiency, PCB area, and heat generation.
Accordingly, VRM multi-phase structures and Dual-Phase DrMOS for improving power density are drawing attention, along with thermal management methods such as package miniaturization and Exposed Top packages.
MPS is responding to high-current, high-power-density AI power design through the MP87595 and MP87597, and is expanding its portfolio to include products supporting 3V to 16V input and up to 8V input.
The expansion of generative AI and LLMs is accelerating competition for data center computing performance.
At the same time, as GPU, AI accelerator, and ASIC performance continues to improve rapidly, power has emerged as a core design challenge for AI systems.
In particular, the current demand for a single socket in the latest AI processors reaches 1,000 to 2,000A, making stable delivery of high current in limited space essential.
As a result, simply expanding the capacity of power semiconductors is not enough to respond, and simultaneously solving power conversion efficiency, PCB area, and heat generation has become a challenge. The focus of AI computing competition is also expanding from computing speed to compact, highly efficient delivery of massive power.
The VRM (Voltage Regulator Module) is a key device for supplying low-voltage, high-current power to AI processors. As the current demand of AI processors increases, a single power stage reaches its limits in handling the total load. Accordingly, a multi-phase structure is needed to distribute the load current.
A multi-phase structure eases current concentration on each power stage. It also helps distribute heat and reduce output ripple. It is also advantageous for improving transient response characteristics.
Because of these characteristics, high-performance AI systems are seeing demand for 16-phase, 24-phase, and even higher power structures. The expansion of multi-phase power structures is becoming necessary.
However, space constraints are a problem. While the integration density and complexity of AI SoC and ASIC devices continue to rise, PCB area cannot be expanded indefinitely. As a result, power design faces the challenge of placing more power stages within limited space while handling greater current at the same time.
In power design for AI systems, the competitive focus is shifting from efficiency alone to greater importance placed on power density. Power density refers to the amount of power handled per unit area, and the ability to manage more power in a limited area is becoming increasingly important.
A technical example addressing these demands is Dual-Phase DrMOS. Dual-Phase DrMOS refers to the integration of 2 power stages, and DrMOS is a structure that combines a driver and MOSFET in a single package.
The purpose of DrMOS is to improve power density. Based on advances in semiconductor process and packaging technology, DrMOS has evolved toward handling more current in the same or smaller space.
Around 2017, the current-handling capability of a 5 mm x 6 mm package was about 70A. Later, as silicon and thermal design technologies advanced, current-handling capability improved to 90A.
After that, the package was reduced to 4 mm x 6 mm while maintaining 90A. This reduction in package size made it possible to place high-current power stages closer to the processor.
In AI power design, improving the integration density of power stages is becoming one axis of change. Extending from that, Dual-Phase DrMOS, which integrates 2 power stages into a single package, has emerged.
Instead of separately placing 2 single-phase DrMOS devices, this product implements 2 phases in a single package. The 5 mm x 5 mm package delivers 60A + 60A, while the 6 mm x 6 mm package delivers 90A + 90A.
Through this configuration, Dual-Phase DrMOS reduces PCB footprint and the number of components. At the same time, it secures high output current.
These advantages become even more significant as the power section of AI systems becomes more complex. Some AI system power sections are configured with 16 phases, 24 phases, or more, and the more complex the AI system, the greater the value of space savings becomes.
Another axis of change in AI power design is input voltage optimization. The standard is a 16V input product, and recently low-voltage Dual-Phase DrMOS supporting up to 8V input has emerged.
The benefits of using a lower input voltage include reduced switching loss and a duty cycle suitable for low-voltage core rails. As a result, it is advantageous for improving power conversion efficiency.
According to MPS test results, under the same conditions, the Dual-Phase DrMOS solution using a low-voltage process showed about 2% better efficiency than the existing Dual DrMOS based on a high-voltage process.
This comparison was made under identical conditions, and the Dual-Phase DrMOS solution using a low-voltage process showed higher efficiency than the existing Dual DrMOS based on a high-voltage process.
The scale of current handled by AI power systems reaches hundreds to several thousand amperes. Accordingly, even a small efficiency difference affects total system power loss, and even a small efficiency difference affects heat generation.
For this reason, the challenge for next-generation AI systems is presented as more than just supplying high current. Important factors for next-generation AI systems are input voltage optimization, power stage structure optimization, and power conversion stage optimization, which must all be considered together.
One problem that becomes more prominent as power density rises is heat. When current-handling capacity increases within the same PCB area, heat per unit area also increases.
Ultimately, improving semiconductor efficiency itself is necessary, and the efficiency with which generated heat is transferred outward determines system performance and also system reliability.
One packaging approach for strengthening thermal management is the Exposed Top package. This package is characterized by an exposed top surface. The difference from existing Overmolded packages is whether the top surface is exposed.
The benefit of the exposed top is that it provides a low-thermal-resistance path from the silicon to the external environment or to a heatsink connection. In an Exposed Top structure, a heatsink can be directly connected to the top of the DrMOS. In addition, TIM can be directly connected to the top of the DrMOS.
This structure adds a cooling path by securing a discharge path from the top of the package in addition to the existing PCB-directed heat dissipation path. Accordingly, it helps alleviate heat concentration on the PCB. It also supports higher power density within limited space.
As a result, the role of semiconductor packages in AI systems is evolving beyond chip protection structures. In AI systems, semiconductor packages are evolving into design elements that determine system power density and thermal performance.
As the competition to improve AI processor performance is expected to continue, the current demand for GPU, SoC, and ASIC devices is likely to increase. However, PCB space has physical limits, and system cooling capacity also has physical limits.
For this reason, the challenge of next-generation AI power design lies in high output current. Next-generation AI power design must consider power stage integration density, PCB area, power conversion efficiency, and thermal management together, and it must be considered as an integrated system rather than as individual elements.
Dual-Phase DrMOS is one technical approach responding to these changes. Dual-Phase DrMOS integrates 2 phases into one package and supplies high current in limited space. It can also improve efficiency and thermal performance by optimizing input voltage and package technology at the same time.
MPS is also expanding its DrMOS portfolio and Intelli-Phase portfolio in response to these changes in AI power architecture.
MPS's MP87595 supports a 3V to 16V input range and supports up to 90A continuous current per phase. On a Dual-Phase basis, it supports up to 180A continuous current, implemented in a single package. Through this, it focused on improving the efficiency of high-current supply for AI processors in limited PCB space.
The MP87597 uses a compact 6 mm x 6 mm package and supports up to 100A continuous current per phase. On a Dual-Phase basis, it supports up to 200A continuous current and supports up to 8V input voltage. This product was designed to address AI power designs with high current and high power density demands.
As AI semiconductor performance advances, the importance of power technology is growing even further. Power is emerging in AI systems not as a peripheral element but as a core technology that determines performance, efficiency, and scalability. In the future, AI competition will expand beyond computing performance to include the ability to supply large-scale power in a compact, highly efficient manner.
MPS has high-integration, high-efficiency power technology and also a broad solutions portfolio. Based on this, the company said it intends to respond to changes and continue supporting the evolution of power architecture for next-generation AI computing.
Source: TECHWORLD · Jeong Tae-hoon, MPS Technical Support Director
Original: https://www.epnc.co.kr/news/articleView.html?idxno=407702
References
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Source: TECHWORLD
Ver originalThis article was summarized and organized by BizCrush based on the original article from TECHWORLD. For exact quotations and full details, please refer to the original article.