TSMC’s ‘CoWoS-L’ Faces Intel’s ‘EMIB-T’ Challenge as Yield Battle Looms
TECHWORLD ·
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As AI chips grow larger, package-size expansion has emerged as a key challenge in 2.5D packaging. TSMC’s CoWoS-L is expected to remain the mainstream technology for large AI chips, but Intel’s EMIB-T is also emerging as an alternative. The key competitive factors are technical capability for handling larger packages and yield, with yield improvement identified as the critical issue for EMIB-T.
As AI semiconductors grow larger, the competitive landscape in the advanced packaging market is shifting rapidly. According to industry sources on the 1st, as AI chips scale up, package-size expansion is emerging as a key challenge in 2.5D packaging. TrendForce forecast that Nvidia’s 2026 high-end GPU shipments will rise by about 30% from a year earlier, while AMD is expected to begin full-scale deployment of its ‘Instinct MI400·MI450’ series from the second half of 2026.
Against this backdrop, TSMC’s ‘CoWoS-L’ is expected to remain the market mainstream, centered on large AI chips. At the same time, Intel’s ‘EMIB-T’ is emerging as an alternative technology.
The key variables in future competition are expected to be the ability to respond to larger package sizes and yield. As it becomes more important to realize larger packages even in 2.5D packaging as AI chips grow, competition in the advanced packaging market is unfolding around these factors.
As CSPs move to expand customized ASICs, Google is pursuing a transition to ‘TPU v7,’ and AWS is pursuing a transition to ‘Trainium v3.’ At the same time, AI chips are seeing both higher computing performance and an increase in the number of HBM stacks they carry.
Amid this trend, the importance of advanced packaging technology is rising. TSMC’s ‘CoWoS-S’ is now widely used in AI chips, and ‘CoWoS-S’ has a structure that connects the compute die and HBM through a silicon interposer.
However, as larger compute dies and greater HBM capacity lead to bigger packages, expanding the size of the silicon interposer has become unavoidable. Because ‘CoWoS-S’ connects the die, HBM, and silicon interposer with micro-bumps, package scaling is followed by a larger silicon interposer.
Analysts say the manufacturing of large silicon interposers is nearing physical limits in this process. As interposer size increases, manufacturing difficulty rises and cost burdens grow, bringing the issue of larger silicon interposers into sharper focus even in the widely used CoWoS-S structure.
CoWoS-S is expected to continue being applied to some product lines. Continued use of CoWoS-S is expected in Microsoft’s ‘Maia 200’ and others. However, a broader shift to CoWoS-L is expected for large AI chips that require more compute dies and HBM.
CoWoS-L has a structure that inserts a high-speed silicon bridge inside the silicon interposer. The connected components are compute dies and HBM. Through this structure, CoWoS-L is characterized by its ability to handle large packages and enable high-speed communication between dies.
Based on these strengths, Nvidia and AMD AI accelerators and Meta’s ‘MTIA 400’ have adopted CoWoS-L. AWS and Microsoft are also expected to apply CoWoS-L from 2027. Considering market trends, TrendForce projected that CoWoS-L will become the mainstream advanced packaging technology for AI chips through 2028.
However, TrendForce cited rising package costs caused by large silicon interposers as a challenge for CoWoS-L. It also pointed to TSMC’s tight production capacity as a constraint. Accordingly, TrendForce said interest is growing in Intel’s EMIB technology, which can reduce dependence on large interposers.
EMIB is a technology that inserts small silicon bridges into the package substrate to connect multiple dies. A defining feature of this technology is that it places silicon bridges only in the necessary areas rather than using a large silicon interposer across the entire package. As a result, it is regarded as advantageous for realizing large packages and also offers cost benefits.
Intel is developing EMIB-T (Embedded Multi-die Interconnect Bridge-Through-silicon via), an advanced version of its existing EMIB technology. The EMIB-T approach is being designed to further miniaturize line/space patterns and further miniaturize micro-bumps. Applying TSVs is also a key element to shorten signal paths.
Google’s 2027 is being discussed as the expected adoption timing for EMIB-T. AWS is also said to be evaluating EMIB-T technology.
However, according to TrendForce analysis, CoWoS-L currently holds the edge in technology maturity and yield. Accordingly, the key factor that will determine EMIB-T’s future spread is identified as yield improvement.
According to industry sources, EMIB substrate yield improved from about 30% in the second quarter of 2026 to about 45% recently. However, the industry’s target is to raise EMIB substrate yield to 50% in the fourth quarter of this year and 60% in the first quarter of 2027.
The main variable for EMIB substrate yield is the difference in thermal expansion coefficients between the ABF substrate and the silicon bridge. During repeated high-temperature processes, precisely placing the silicon bridge cavity inside the substrate is a challenge, and maintaining surface flatness is also a challenge. In addition, if bubbles form in the non-conductive film (NCF) used for bonding the underside of the bridge, adhesion weakens.
Ultimately, the conditions for EMIB-T to establish itself as an alternative to CoWoS-L are securing technical performance in fine wiring and TSVs, as well as securing stable yield in mass production.
The competitive scope around EMIB-T is expanding beyond the packaging technology contest between Intel and TSMC and into the advanced package substrate area that supports it. Competition in technology development among advanced package substrate suppliers is also intensifying at the same time.
Amid this trend, Samsung Electro-Mechanics is pursuing entry into the EMIB-T-related market. LG Innotek is also pursuing entry into the EMIB-T-related market.
As a result, competition among domestic and overseas package substrate companies is expected to begin in earnest. As the number of competing players increases, the market structure surrounding EMIB-T is also becoming more intense.
A semiconductor industry expert said that as AI chips become larger and HBM capacity increases, the impact of packaging technology on performance, productivity, and cost will grow. Another semiconductor industry expert predicted that competition over CoWoS-L and EMIB-T technology, as well as the race to secure yield for advanced package substrates, will intensify further.
Source: TECHWORLD · Park Gyu-chan
Original: https://www.epnc.co.kr/news/articleView.html?idxno=407610
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Source: TECHWORLD
Ver originalThis article was summarized and organized by BizCrush based on the original article from TECHWORLD. For exact quotations and full details, please refer to the original article.